VHDL实现8选1数据选择器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux8 IS
	PORT(data:IN STD_LOGIC_VECTOR(0 TO 7);
		addr:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
		output:OUT STD_LOGIC);
END mux8;
ARCHITECTURE mux8_behavior OF mux8 IS
BEGIN
	PROCESS(addr,data)
	BEGIN
		CASE addr IS
			WHEN "000" => output<=data(0);
			WHEN "001" => output<=data(1);
			WHEN "010" => output<=data(2);
			WHEN "011" => output<=data(3);
			WHEN "100" => output<=data(4);
			WHEN "101" => output<=data(5);
			WHEN "110" => output<=data(6);
			WHEN "111" => output<=data(7);
			WHEN OTHERS => NULL;
		END CASE;
	END PROCESS;
END mux8_behavior;