HDLbits Exams/ece241 2013 q4

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    reg [2:0] state;
    reg [2:0] next;
    reg ndfr;
    
    always@(*)begin
        if(reset)begin
            next = 3'b111;
            ndfr = 1;
        end else begin
            case(s)
                3'b111: next = 3'b000;
                3'b011: next = 3'b001;
                3'b001: next = 3'b011;
                3'b000: next = 3'b111;
            endcase
            case(s)
                3'b000: ndfr = 1;
                default: 
                    ndfr = (state == next) ? dfr : ((state > next) ? 0 : 1);
            endcase
        end
    end
    
    always@(posedge clk)begin
        state <= next;
        dfr <= ndfr;
    end
    
    assign {fr3, fr2, fr1} = state;

endmodule