blocks|key|2359666|text|除以3等于乘以1/3+(=0.33333)。0.3333可以表示为两个或两个以上的加法(取决于所需的精度)(左)移位输入值。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|2359667|input*2%5E-a+%2B+input*2%5E-b+%2B+input*2%5E-c+...|code-block|syntax|javascript|2359668|只要为a，b，c，.找到合适的值.|2359669|这适用于(几乎)所有部门。|2359670|entityMap^0|0|0|0|0^^$0|@$1|2|3|4|5|6|7|M|8|@]|9|@]|A|$]]|$1|B|3|C|5|D|7|N|8|@]|9|@]|A|$E|F]]|$1|G|3|H|5|6|7|O|8|@]|9|@]|A|$]]|$1|I|3|J|5|6|7|P|8|@]|9|@]|A|$]]|$1|K|3|-4|5|6|7|Q|8|@]|9|@]|A|$]]]|L|$]]

Dividing by 3 is the same as multiplying by 1/3 (=0.33333). 0.3333 can be expressed as an addition of two or more (depending on the needed accuracy) (left) shifted input values. 

<pre><code>input*2^-a + input*2^-b + input*2^-c ...
</code></pre>

Just find suitable values for a, b, c, ...

This works for (almost) all divisions.

blocks|key|2359698|text|下面是Hacker‘some’some中一些代码的VHDL翻译。它使用仅使用移位、加法和乘积的常量3除以无符号整数3(也可以简化为移位和加法)。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|2359699|--+q+is+quotient,+d+is+dividend
q+:=+(d+srl+2)+%2B+(d+srl+4);+--+q+=+d*0.0101+(approx)
q+:=+q+%2B+(q+srl+4);+--+q+=+d*0.01010101
q+:=+q+%2B+(q+srl+8);
q+:=+q+%2B+(q+srl+16);
r+:=+resize(d+-+q+*+3,+32);+--+0+<=+r+<=+15.
q+:=+resize(q+%2B+(5+*+(r+%2B+1)+srl+4),+32);|code-block|syntax|javascript|2359700|entityMap^0|0|0^^$0|@$1|2|3|4|5|6|7|I|8|@]|9|@]|A|$]]|$1|B|3|C|5|D|7|J|8|@]|9|@]|A|$E|F]]|$1|G|3|-4|5|6|7|K|8|@]|9|@]|A|$]]]|H|$]]

The following is a VHDL translation of some code from Hank Warren’s Hacker’s Delight. It divides an unsigned integer by the constant value 3 using only shifts, additions, and multiplications by the constant values 3 and 5 (which can also be reduced to shifts and additions).

<pre><code>-- q is quotient, d is dividend
q := (d srl 2) + (d srl 4); -- q = d*0.0101 (approx)
q := q + (q srl 4); -- q = d*0.01010101
q := q + (q srl 8);
q := q + (q srl 16);
r := resize(d - q * 3, 32); -- 0 &lt;= r &lt;= 15.
q := resize(q + (5 * (r + 1) srl 4), 32);
</code></pre>

blocks|key|1893765|text|如果长度为3的无符号值需要整数除以3+(x+/+3)的确切结果，则可以使用截断整数操作。1/3的常量应该是长度LEN+%2B+1，并且应该添加1。然后可以在以后使用截断。伪码为：|type|unstyled|depth|inlineStyleRanges|offset|length|style|CODE|entityRanges|data|1893766|C+=+2+**+(LEN+%2B+1)+/+3+%2B+1
y+=+(x+*+C)+/+2+**+(LEN+%2B+1)|code-block|syntax|javascript|1893767|显示和测试所有值的算法的Python函数是：|1893768|def+div_by_3_test(LEN):
++++DIVISOR+=+3
++++C+=+2+**+(LEN+%2B+1)+//+DIVISOR+%2B+1
++++for+x+in+range(2+**+LEN):
++++++++if+(x+*+C)+//+2+**+(LEN+%2B+1)+!=+x+//+DIVISOR:+exit('Failed')+|1893769|实现此功能的VHDL模块如下：|1893770|library+ieee;
use+ieee.std_logic_1164.all;
use+ieee.numeric_std.all;

entity+div_by_3+is
++generic(
++++LEN+:+natural+:=+12);
++port(
++++x_i+++:+in++std_logic_vector(LEN+-+1+downto+0);
++++y_o+++:+out+std_logic_vector(LEN+-+1+downto+0));
end+entity;

architecture+syn+of+div_by_3+is
++--+Constant+to+multiply,+basically+1/3,+but+adding+1+to+avoid+error
++constant+C+:+std_logic_vector(LEN+-+1+%2B+1+downto+0)+:=
++++std_logic_vector(to_unsigned(2+**+(LEN+%2B+1)+/+3+%2B+1,+LEN+%2B+1));
++--+Intermediate,+with+length+as+2+*+LEN+%2B+1
++signal+t+:+std_logic_vector(2+*+LEN+%2B+1+-+1+downto+0);
begin
++--+Intermediate+with+full+length+result
++t+<=+std_logic_vector(unsigned(C)+*+unsigned(x_i));
++--+Result+after+truncation+for+division+by+LEN+%2B+1
++y_o+<=+t(2+*+LEN+%2B+1+-+1+downto+LEN+%2B+1);
end+architecture;|1893771|其优点是，仅使用一个LEN位数乘法，就可以在一个周期内将一个2+*+LEN+%2B+1位数除以3。|1893772|可以添加寄存器以允许高速设计的流水线。|1893773|请注意，对于任何除数都可以使用类似的方案，但是C的长度必须是LEN+%2B+ceil(log2(DIVISOR))，并相应地缩放C。关于数学基础，请参阅https://math.stackexchange.com/q/2444306/275980。|1893774|entityMap|0|LINK|mutability|MUTABLE|url|https://math.stackexchange.com/q/2444306/275980^0|K|5|18|3|1J|7|0|0|0|0|0|0|A|3|U|B|0|0|N|1|U|P|1Q|1|22|1B|0|0^^$0|@$1|2|3|4|5|6|7|16|8|@$9|17|A|18|B|C]|$9|19|A|1A|B|C]|$9|1B|A|1C|B|C]]|D|@]|E|$]]|$1|F|3|G|5|H|7|1D|8|@]|D|@]|E|$I|J]]|$1|K|3|L|5|6|7|1E|8|@]|D|@]|E|$]]|$1|M|3|N|5|H|7|1F|8|@]|D|@]|E|$I|J]]|$1|O|3|P|5|6|7|1G|8|@]|D|@]|E|$]]|$1|Q|3|R|5|H|7|1H|8|@]|D|@]|E|$I|J]]|$1|S|3|T|5|6|7|1I|8|@$9|1J|A|1K|B|C]|$9|1L|A|1M|B|C]]|D|@]|E|$]]|$1|U|3|V|5|6|7|1N|8|@]|D|@]|E|$]]|$1|W|3|X|5|6|7|1O|8|@$9|1P|A|1Q|B|C]|$9|1R|A|1S|B|C]|$9|1T|A|1U|B|C]]|D|@$9|1V|A|1W|1|1X]]|E|$]]|$1|Y|3|-4|5|6|7|1Y|8|@]|D|@]|E|$]]]|Z|$10|$5|11|12|13|E|$14|15]]]]

If the exact result of integer division by 3 (<code>x / 3</code>) is required for an unsigned value of length <code>LEN</code>, then truncating integer operations can be used with a little trick. The constant for <code>1/3</code> should be of length <code>LEN + 1</code> and 1 should be added. Truncation can then be used afterwards. Pseudo code as:

<pre><code>C = 2 ** (LEN + 1) / 3 + 1
y = (x * C) / 2 ** (LEN + 1)
</code></pre>

A Python function that shows and tests the algorithm for all values is:

<pre><code>def div_by_3_test(LEN):
 DIVISOR = 3
 C = 2 ** (LEN + 1) // DIVISOR + 1
 for x in range(2 ** LEN):
 if (x * C) // 2 ** (LEN + 1) != x // DIVISOR: exit('Failed') 
</code></pre>

A VHDL module that implements this as:

<pre><code>library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity div_by_3 is
 generic(
 LEN : natural := 12);
 port(
 x_i : in std_logic_vector(LEN - 1 downto 0);
 y_o : out std_logic_vector(LEN - 1 downto 0));
end entity;

architecture syn of div_by_3 is
 -- Constant to multiply, basically 1/3, but adding 1 to avoid error
 constant C : std_logic_vector(LEN - 1 + 1 downto 0) :=
 std_logic_vector(to_unsigned(2 ** (LEN + 1) / 3 + 1, LEN + 1));
 -- Intermediate, with length as 2 * LEN + 1
 signal t : std_logic_vector(2 * LEN + 1 - 1 downto 0);
begin
 -- Intermediate with full length result
 t &lt;= std_logic_vector(unsigned(C) * unsigned(x_i));
 -- Result after truncation for division by LEN + 1
 y_o &lt;= t(2 * LEN + 1 - 1 downto LEN + 1);
end architecture;
</code></pre>

The advantage is that a division by 3 of an <code>LEN</code> bit number can be made in one cycle using only a single <code>2 * LEN + 1</code> bit multiplication.

Registers may be added to allow pipeline for high speed design.

Note that a similar scheme is possible for any divisor, but length of <code>C</code> must then be <code>LEN + ceil(log2(DIVISOR))</code>, with <code>C</code> scaled accordingly. Please see <a href="https://math.stackexchange.com/q/2444306/275980">https://math.stackexchange.com/q/2444306/275980</a> regarding the mathematical foundation.

blocks|key|1135981|text|正如dieli提到的，乘以0.333333。|type|unstyled|depth|inlineStyleRanges|entityRanges|data|1135982|然而，与其使用2的几个负幂(即a，b，c，.)只需将1/3乘以2的大幂，例如2%5E24+*+(1/3)+=+5592405。在将时钟周期乘以5592405之后，只需除以2%5E24。|1135983|B=(时钟周期)*5592405|1135984|结果=+B/2%5E24|1135985|B的大小将取决于时钟周期的最大大小，并且可以由|1135986|B=整数的最大寄存器大小((log10((最大时钟周期大小)*5592405)/log10(2))%2B+0.5)|1135987|entityMap^0|0|0|0|0|0|0^^$0|@$1|2|3|4|5|6|7|N|8|@]|9|@]|A|$]]|$1|B|3|C|5|6|7|O|8|@]|9|@]|A|$]]|$1|D|3|E|5|6|7|P|8|@]|9|@]|A|$]]|$1|F|3|G|5|6|7|Q|8|@]|9|@]|A|$]]|$1|H|3|I|5|6|7|R|8|@]|9|@]|A|$]]|$1|J|3|K|5|6|7|S|8|@]|9|@]|A|$]]|$1|L|3|-4|5|6|7|T|8|@]|9|@]|A|$]]]|M|$]]

As mentioned by dieli, multiply by 0.333333.
However, instead of using several negative powers of 2 (i.e. a, b, c,..) just multiply 1/3 by some large power of 2, e.g. 2^24 * (1/3) = 5592405. After multiplying the clock cycles and 5592405, just divide by 2^24.
B = (clock cycles)*5592405
result = B/2^24
The size of B would depend the maximum size of clock cycles and can be computed by
maximum register size for B = integer of ( (log10((max size of clock cycles)*5592405)/log10(2)) + 0.5)

I'm working on a project that is to make a simple music player on an FPGA. It takes a music file of a specified format from the PC and plays it out loud in loops. 

We need to implement the standard note lengths, i.e. Quaver for half a beat, Minim for 2 beats, etc. Currently we have a table of the lengths of a beat in numbers of clock cycles at various BPM values. We need to multiply them by these note lengths to yield the correct clock cycles. The only problem is Tuplet, which is a third of a full beat.

Without implementing a full-blown divider circuit, are there any maths tricks one can do to divide, approximately, an integer by 3?

Easy way of dividing an integer by 3

翻译质量差，导致语言生硬或混乱。

没有提供实际的解决方法或示例。

解答不清晰，无法理解或解决问题。

页面排版不美观，阅读体验差。

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我正在做一个项目，就是在FPGA上制作一个简单的音乐播放器。它从PC上获取一个指定格式的音乐文件，并在循环中大声播放。我们需要实现标准的音符长度，即，Quaver为半拍，Minim为2拍，等等。目前，我们有一个表，在不同的BPM值的时钟周期数的节拍长度。我们需要把它们乘以这些音符的长度，才能得到正确的时钟周期。唯一的问...

问整数除以3的简单方法
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问整数除以3的简单方法EN