在VHDL中有没有一种外部名称引用泛型的方法？

package my_pkg is
  generic (WIDTH : natural := 8);
  signal my_signal : std_logic_vector(WIDTH-1 downto 0);
end package my_pkg;

library ieee;
use ieee.std_logic_1164.all;
use work.my_pkg.all; -- 引用包声明

entity top_entity is
  generic (WIDTH : natural := 16);
  port (
    clk : in std_logic;
    data_in : in std_logic_vector(WIDTH-1 downto 0);
    data_out : out std_logic_vector(WIDTH-1 downto 0)
  );
end entity top_entity;

architecture rtl of top_entity is
begin
  -- 使用外部名称引用泛型
  process(clk)
    variable local_data : std_logic_vector(WIDTH-1 downto 0) := my_signal; 
  begin
    -- 进行其他操作
  end process;
end architecture rtl;