在Verilog中高效合成4对1功能

module mux_4to1(input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [1:0] sel, output reg [3:0] out);
always @(*) begin
case (sel)
2'b00 : out = a;
2'b01 : out = b;
2'b10 : out = c;
2'b11 : out = d;
endcase
end
endmodule

module mux_4to1(input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [1:0] sel, output reg [3:0] out);
always @(*) begin
if (sel == 2'b00) out = a;
else if (sel == 2'b01) out = b;
else if (sel == 2'b10) out = c;
else if (sel == 2'b11) out = d;
end
endmodule

module mux_4to1(input [3:0] a, input [3:0] b, input [3:0] c, input [3:0] d, input [1:0] sel, output reg [3:0] out);
always @(*) begin
out = {a, b, c, d}[4*sel +: 4];
end
endmodule