如何创建有组件而无包体的VHDL封装？

component MyComponent
  port (
    input1 : in std_logic;
    input2 : in std_logic;
    output1 : out std_logic
  );
end component;

entity MyWrapper is
  port (
    input1 : in std_logic;
    input2 : in std_logic;
    output1 : out std_logic
  );
end entity;

architecture Behavioral of MyWrapper is
  component MyComponent
    port (
      input1 : in std_logic;
      input2 : in std_logic;
      output1 : out std_logic
    );
  end component;

  -- 实例化组件
  signal internal_signal : std_logic;
begin
  my_component_inst : MyComponent
    port map (
      input1 => input1,
      input2 => input2,
      output1 => internal_signal
    );

  -- 连接内部信号到输出端口
  output1 <= internal_signal;
end architecture;