如何在VHDL中获得n个‘1’的二进制数？

library ieee;
use ieee.std_logic_1164.all;

entity GenerateBinary is
  generic (
    N : positive := 8  -- 设置二进制数的位数，默认为8位
  );
  port (
    output : out std_logic_vector(N-1 downto 0)
  );
end GenerateBinary;

architecture Behavioral of GenerateBinary is
begin
  process
    variable count : natural := 0;
    variable binary : std_logic_vector(N-1 downto 0);
  begin
    binary := (others => '0');  -- 初始化二进制数为全0
    for i in binary'range loop
      if count < N then
        binary(i) := '1';  -- 将当前位设置为'1'
        count := count + 1;  -- 计数器加1
      else
        exit;  -- 达到指定的'1'的个数后退出循环
      end if;
    end loop;
    output <= binary;  -- 输出生成的二进制数
    wait;
  end process;
end Behavioral;