用VHDL产生2个时钟脉冲

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ClockGenerator is
    port (
        clk_in : in std_logic;
        clk_out1 : out std_logic;
        clk_out2 : out std_logic
    );
end entity ClockGenerator;

architecture Behavioral of ClockGenerator is
    signal counter : unsigned(1 downto 0) := (others => '0');
    constant clk_divider : unsigned(1 downto 0) := "01"; -- 时钟分频因子，这里设置为2

begin
    process(clk_in)
    begin
        if rising_edge(clk_in) then
            counter <= counter + 1;
            if counter = clk_divider then
                clk_out1 <= not clk_out1;
                clk_out2 <= not clk_out2;
            end if;
        end if;
    end process;
end architecture Behavioral;