串口通信控制器的Verilog HDL实现（一） 顶层模块

module uart_top(
sys_clk_50MHz,rst_p,txd,rxd,LED,button_n,button_s
    );
 input sys_clk_50MHz;
 input rst_p;
 input rxd;
 output txd;
 input button;
 input button_s;
 output [7:0]LED;
 reg [7:0]LED;
 wire bclk;
 wire [7:0]rx_dout;
 wire ready;
 reg [7:0]din;
 wire tx_ready;
 reg tx_cmd;
 baud_gen u1(
.clk_50MHz(sys_clk_50MHz),
.rst_p(rst_p),
.bclk(bclk)
);
reg [2:0]bv1,bv2;
wire bv1_posedge,bv2_posedge;
always @(posedge bclk)
begin
bv1<={bv1[1:0],button_n};
bv2<={bv2[1:0],rx_ready};
end
assign bv1_posedge=(!bv1[2])&bv1[1];
assign bv2_posedge=(!bv2[2])&bv2[1];
always@(posedge bclk)
begin
if(button_s==1'b1)
begin
din<=48;//ASCII   0
tx_cmd<=1'b0;
end
else
begin
if(bv1_posedge==1'b1)
begin
din<=din+1'b1;
tx_cmd<=1'b1&tx_ready;
end
else
begin
din<=din;
tx_cmd<=1'b0;
end
end
end
always@(posedge bclk)
begin
if(bv2_posedge==1'b1)
begin
LED<=rx_dout;
end
end
uart_tx u2(
.bclk(bclk),
.reset(rst_p),
.tx_din(din),
.tx_cmd(tx_cmd),
.tx_ready(tx_ready),
.txd(txd)
);
uart_rx u3(
.bclk(bclk),
.reset(rst_p),
.rxd(rxd),
.rx_out(rx_out),
.rx_ready(rx_ready)
);
endmodule