opt_design [-retarget] [-propconst] [-sweep] [-bram_power_opt] [-remap]
[-resynth_area] [-resynth_seq_area] [-directive <arg>] [-muxf_remap]
[-hier_fanout_limit <arg>] [-bufg_opt] [-control_set_merge] [-quiet] [-verbose]
Retargeting replaces one cell type with another to ease optimization. For example, a MUXF7
replaced by a LUT3 can be combined with other LUTs. In addition, simple cells such as
inverters are absorbed into downstream logic.
Constant Propagation propagates constant values through logic, which results in:
• Eliminated logic:
For example, an AND with a constant 0 input
• Reduced logic:
For example, A 3-input AND with a constant 1 input is reduced to a 2-input AND.
• Redundant logic:
For example, A 2-input OR with a logic 0 input is reduced to a wire.
Sweep removes cells that have no loads.
Block RAM Power Optimization enables power optimization on block RAM cells including:
• Changing the WRITE_MODE on unread ports of true dual-port RAMs to NO_CHANGE.
• Applying intelligent clock gating to block RAM outputs.
Remap combines multiple LUTs into a single LUT to reduce the depth of the logic.
Resynth Area performs re-synthesis in area mode to reduce the number of LUTs.
Remaps MUXF7, MUXF8, and MUXF9 primitives to LUT3 to improve route-ability.
Reduce the drivers of logically-equivalent control signals to a single driver. This is like a reverse fanout replication, and results in nets that are better suited for module-based replication.
Logic optimization conservatively inserts global clock buffers on clock nets and high-fanout non-clock nets such as device-wide resets.
For 7 series designs, clock buffers are inserted as long as 12 total global clock buffers arenot exceeded.
For UltraScale designs, there is no limit for clock buffers inserted on clock nets.
For non-clock nets:
• Global clock buffers are only inserted as long as 24 total clock buffers are not
exceeded, not including BUFG_GT buffers.
• The fanout must be above 25,000.
For fabric-driven clock nets, the fanout must be 30 or greater.
Net drivers with fanout greater than the specified limit, provided as an argument with this option, will be replicated according to the logical hierarchy.
For each hierarchical instance driven by the high-fanout net, if the fanout within the hierarchy is greater than the specified limit, then the net within the hierarchy is driven by a replica of the driver of the high-fanout net
Runs multiple passes of optimization.
Runs multiple passes of optimization with emphasis on reducing combinational logic.
Runs the default logic optimization flow and includes LUT remapping to reduce logic levels.
Runs multiple passes of optimization with emphasis on reducing registers and related combinational logic.
Runs minimal passes of optimization, trading design performance for faster run time.
Runs all the default opt_design optimizations except block RAM Power Optimization.
Same as the Explore directive but includes the Remap optimization.
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