Retargetingreplaces one cell type with another to ease optimization. For example, a MUXF7
replaced by aLUT3 can be combined with other LUTs. In addition, simple cells such as
inverters areabsorbed into downstream logic.
ConstantPropagation propagates constant values through logic, which results in:
For example, anAND with a constant 0 input
• Reduced logic:
For example, A3-input AND with a constant 1 input is reduced to a 2-input AND.
For example, A2-input OR with a logic 0 input is reduced to a wire.
Sweep removescells that have no loads.
Block RAM PowerOptimization enables power optimization on block RAM cells including:
• Changing the WRITE_MODE on unread ports of true dual-port RAMs to NO_CHANGE.
• Applyingintelligent clock gating to block RAM outputs.
Remap combinesmultiple LUTs into a single LUT to reduce the depth of the logic.
Resynth Areaperforms re-synthesis in area mode to reduce the number of LUTs.
Remaps MUXF7,MUXF8, and MUXF9 primitives to LUT3 to improve route-ability.
Reduce thedrivers of logically-equivalent control signals to a single driver. This islike a reverse fanout replication, and results in nets that are better suitedfor module-based replication.
Logicoptimization conservatively inserts global clock buffers on clock nets andhigh-fanout non-clock nets such as device-wide resets.
For 7 seriesdesigns, clock buffers are inserted as long as 12 total global clock buffersarenot exceeded.
For UltraScale designs,there is no limit for clock buffers inserted on clock nets.
• Global clockbuffers are only inserted as long as 24 total clock buffers are not
exceeded, notincluding BUFG_GT buffers.
• The fanoutmust be above 25,000.
For fabric-drivenclock nets, the fanout must be 30 or greater.
Net drivers withfanout greater than the specified limit, provided as an argument with thisoption, will be replicated according to the logical hierarchy.
For each hierarchicalinstance driven by the high-fanout net, if the fanout within the hierarchy isgreater than the specified limit, then the net within the hierarchy is drivenby a replica of the driver of the high-fanout net.
Runs multiplepasses of optimization.
Runs multiplepasses of optimization with emphasis on reducing combinational logic.
Runs the defaultlogic optimization flow and includes LUT remapping to reduce logic levels.
Runs multiplepasses of optimization with emphasis on reducing registers and related combinationallogic.
Runs minimalpasses of optimization, trading design performance for faster run time.
Runs all thedefault opt_design optimizations except block RAMPower Optimization.
Same as the Explore directive but includes the Remap optimization.
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