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FPGA程序升级续

Startup原语及其约束

fpga掉电丢失,一般使用外部flash存储代码,flash有spi、bpi、qspi等接口,外部存储器的时钟管脚一般与fpga的CCLK_0连接,当使用远程更新时,首先fpga内部有控制flash的驱动(即逻辑控制flash时序),当然flash时钟也需要控制了,但这时时钟管脚已经连接到CCLK_0,那该如何操作啊,你直接约束分配管脚试试,是通不过的,这时STARTUPE2就派上用场了,那该如何使用啊,如下(K7系列verilog):

STARTUPE2 #( .PROG_USR("FALSE"), // Activate program event security feature. Requires encrypted bitstreams. .SIM_CCLK_FREQ(0.0) // Set the Configuration Clock Frequency(ns) for simulation ) STARTUPE2_inst ( .CFGCLK(), // 1-bit output: Configuration main clock output .CFGMCLK(), // 1-bit output: Configuration internal oscillator clock output .EOS(), // 1-bit output: Active high output signal indicating the End Of Startup. .PREQ(), // 1-bit output: PROGRAM request to fabric output .CLK(0), // 1-bit input: User start-up clock input .GSR(0), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name) .GTS(0), // 1-bit input: Global 3-state input (GTS cannot be used for the port name) .KEYCLEARB(1), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM) .PACK(1), // 1-bit input: PROGRAM acknowledge input .USRCCLKO(flash_clk), // 1-bit input: User CCLK input .USRCCLKTS(0), // 1-bit input: User CCLK 3-state enable input .USRDONEO(1), // 1-bit input: User DONE pin output control .USRDONETS(1) // 1-bit input: User DONE 3-state enable outpu );

其中flash_clk就是你时序控制的flash时钟信号,连接到这就行了,其它的不需要改动,也无需约束此管脚(因为此管脚不需要在顶层作为输出信号了)。

约束如下:

set cclk_delay 6.7

# Following are the SPI device parameters

# Max Tco

set tco_max 7

# Min Tco

set tco_min 1

# Setup time requirement

set tsu 2

# Hold time requirement

set th 3

# Following are the board/trace delay numbers

# Assumption is that all Data lines are matched

set tdata_trace_delay_max 0.25

set tdata_trace_delay_min 0.25

set tclk_trace_delay_max 0.2

set tclk_trace_delay_min 0.2

### End of user provided delay numbers

# This is to ensure min routing delay from SCK generation to STARTUP input

# User should change this value based on the results

# Having more delay on this net reduces the Fmax

# Following constraint should be commented when the STARTUP block is disabled

set_max_delay 1.5 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO] -datapath_only

set_min_delay 0.1 -from [get_pins -hier *SCK_O_reg_reg/C] -to [get_pins -hier *USRCCLKO]

# Following command creates a divide by 2 clock

# It also takes into account the delay added by the STARTUP block to route the CCLK

# This constraint is not needed when the STARTUP block is disabled

# The following constraint should be commented when the STARTUP block is disabled

create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_pins -hierarchical *USRCCLKO] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay]

# Enable the following constraint when STARTUP block is disabled

#create_generated_clock -name clk_virt -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}

# Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge

# Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk

set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_IO] -clock_fall;

set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_IO] -clock_fall;

set_multicycle_path 2 -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]

set_multicycle_path 1 -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]]

# Data is captured into SPI on the following rising edge of SCK

# Data is driven by the IP on alternate rising_edge of the ext_spi_clk

set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_IO];

set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min -$th - $tclk_trace_delay_max] [get_ports IO*_IO];

set_multicycle_path 2 -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck

set_multicycle_path 1 -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck

本文分享自微信公众号 - 瓜大三哥(xiguazai_tortoise),作者:xiguazaitortoise

原文出处及转载信息见文内详细说明,如有侵权,请联系 yunjia_community@tencent.com 删除。

原始发表时间:2020-03-16

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