SPI

                        _   _   _   _   _   _         _   _   _
              inClk  _/ \_/ \_/ \_/ \_/ \_/ \.....\_/ \_/ \_/ \_
                     ___                                   _____
    inReset_EnableB     \_________________________________/
                     _____                                   ___
          outSpiCsB       \_________________________________/
                     _______ ___
   inData8Send[7:0]  _______XD8SXXX...
                                 ___ ___ ___       ___ _________
          inSpiMosi             XD7_XD6_XD5_X.....XD0_X_________
                     ___________   _   _   _    _    ___________
          outSpiClk             \_/ \_/ \_/ \.....\_/
                                                     ___________
outData8Receive[7:0]           XD8SX               XXXD8R*D8SX___

library ieee;
--Library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
--use UNISIM.vcomponents.all;

entity SpiSerDes is
  port 
  (
    -- SerDes clock and control signals
    inClk           : in  std_logic;  -- System clock. Fmax <= SPI peripheral Fmax.
    inReset_EnableB : in  std_logic;  -- Active-high, synchronous reset.
    inStartTransfer : in  std_logic;  -- Active-high, initiate transfer of data
    outTransferDone : out std_logic;  -- DONE='1' when transfer is done

    -- Parallel data ports
    inData8Send     : in  std_logic_vector(7 downto 0); -- Sent to SPI device
    outData8Receive : out std_logic_vector(7 downto 0); -- Received from SPI device

    -- SPI ports and tristate control - Connect these to the SPI bus
    outSpiCsB       : out std_logic;  -- SPI chip-select to SPI device 
                                      -- or all SPI outputs control enable
    outSpiClk       : out std_logic;  -- SPI clock to SPI device
    outSpiMosi      : out std_logic;  -- SPI master-out, slave-in to SPI device
    inSpiMiso       : in  std_logic   -- SPI master-in, slave-out from SPI device
  );
end SpiSerDes;

architecture behavioral of SpiSerDes is

  -- Constants
  constant  cShiftCountInit : std_logic_vector(8 downto 0)  := B"000000001";

  -- Registers
  signal    regShiftCount   : std_logic_vector(8 downto 0)  := cShiftCountInit;
  signal    regShiftData    : std_logic_vector(7 downto 0)  := B"00000000";
  signal    regSpiCsB       : std_logic                     := '1';
  signal    regSpiMosi      : std_logic                     := '1';
  signal    regTransferDoneDelayed  : std_logic             := '1';

  -- Signals
  signal    intTransferDone : std_logic;

  -- Attributes
  attribute clock_signal    : string;
  attribute clock_signal    of inClk : signal is "yes";

begin
  -- Internal signals
  intTransferDone <= regShiftCount(0);

  -- TransferDone delayed by half clock cycle
  processTransferDone : process (inClk)
  begin
    if (falling_edge(inClk)) then
      regTransferDoneDelayed  <= intTransferDone;
    end if;
  end process processTransferDone;

  -- SPI chip-select (active-Low) is always inverse of inReset_EnableB.
  processSpiCsB : process (inClk)
  begin
    if (rising_edge(inClk)) then
      regSpiCsB <= inReset_EnableB;
    end if;
  end process processSpiCsB;

  -- Track transfer of serial data with barrel shifter.
  processShiftCount : process (inClk)
  begin
    if (rising_edge(inClk)) then
      if (inReset_EnableB='1') then
        regShiftCount <= cShiftCountInit;
      elsif ((intTransferDone='0') or (inStartTransfer='1')) then
        -- Barrel shift (rotate right)
        regShiftCount <= regShiftCount(0) & regShiftCount(8 downto 1);
      end if;
    end if;
  end process processShiftCount;

  -- Simultaneous serialize outgoing data & deserialize incoming data. MSB first
  processShiftData : process (inClk)
  begin
    if (rising_edge(inClk)) then
      if (intTransferDone='0') then
        -- SHIFT-left while not outTransferDone
        regShiftData  <= regShiftData(6 downto 0) & inSpiMiso;
      elsif (inStartTransfer='1') then
        -- Load data to start a new transfer sequence from a done state
        regShiftData  <= inData8Send;
      end if;
    end if;
  end process processShiftData;

  -- SPI MOSI register outputs on falling edge of inClk.  MSB first.
  processSpiMosi : process (inClk)
  begin
    if (falling_edge(inClk)) then
      if (inReset_EnableB='1') then
        regSpiMosi  <= '1';
      elsif (intTransferDone='0') then
        regSpiMosi  <= regShiftData(7);
      end if;
    end if;
  end process processSpiMosi;

  -- Assign outputs
      outSpiClk       <= (inClk or intTransferDone or regTransferDoneDelayed);
      outSpiCsB       <= regSpiCsB;
      outSpiMosi      <= regSpiMosi;
      outTransferDone <= intTransferDone;
      outData8Receive <= regShiftData;

end behavioral;