【UVM COOKBOOK】Sequences||激励

// 
// DO NOT USE THIS PATTERN - Supplied as an example of what NOT to do 
// 
// Parent sequence body method running child sub_sequences within a fork join_any 
task body(); 
// 
// Code creating and randomizing the child sequences 
// 
 fork 
  seq_A.start(m_sequencer); 
  seq_B.start(m_sequencer); 
  seq_C.start(m_sequencer); 
 join_any 
// First past the post completes the fork and disables it 
 disable fork; 
// Assuming seq_A completes first - seq_B and seq_C will be terminated in an indeterminate 
// way, locking up the sequencer 

// 
// DO NOT USE THIS PATTERN - Supplied as an example of what NOT to do 
// 
// Inside sequence_As body method 
// 
task body(); 
  // Initialise etc 
 fork 
// The body code including other sequences and sequence_items 
// ... 
 join_none 
endtask body; 
// 
// The body task exits immediately, in the controlling thread the idea is that sequence_A executes 
// in parallel with other sequences: 
// 
task run_phase( uvm_phase phase ); 
// .... 
 sequence_A_h.start(m_sequencer); 
  another_seq_h.start(m_sequencer);  // This sequence executes in parallel with sequence_A_h 
// ... 
// The way to achieve the desired functionality is to remove the fork join_none from sequence_A 
// and to fork join the two sequences in the control thread: 
// 
task run; 
// .... 
 fork 
  sequence_A_h.start(m_sequencer); 
  another_seq_h.start(m_sequencer); 
 join 
// .... 

// 
// This sequence shows how data members can be set to rand values 
// to allow the sequence to either be randomized or set to a directed 
// set of values in the controlling thread 
// 
// The sequence reads one block of memory (src_addr) into a buffer and then 
// writes the buffer into another block of memory (dst_addr). The size 
// of the buffer is determined by the transfer size 
// 
class mem_trans_seq extends bus_seq_base; 
 `uvm_object_utils(mem_trans_seq) 
// Randomised variables 
 rand logic[31:0] src_addr; 
 rand logic[31:0] dst_addr; 
 rand int transfer_size; 
// Internal buffer 
 logic[31:0] buffer[]; 
// Legal limit on the page size is 1023 transfers 
// 
// No point in doing a transfer of 0 transfers 
// 
 constraint page_size { 
  transfer_size inside {[1:1024]}; 
 } 
// Addresses need to be aligned to 32 bit transfers 
 constraint address_alignment {
   src_addr[1:0] == 0; 
  dst_addr[1:0] == 0; 
 } 
 function new(string name = "mem_trans_seq"); 
  super.new(name); 
 endfunction 
 task body; 
  bus_seq_item req = bus_seq_item::type_id::create("req"); 
  logic[31:0] dst_start_addr = dst_addr; 
    buffer = new[transfer_size]; 
  `uvm_info("run:", $sformatf("Transfer block of %0d words from %0h-%0h to %0h-%0h", transfer_size, src_addr, src_addr+((transfer_size-1)*4), dst_addr, dst_addr+((transfer_size-1)*4)), UVM_LOW) 
// Fill the buffer 
  for(int i = 0; i < transfer_size-1; i++) begin 
   start_item(req); 
   if(!req.randomize() with {addr == src_addr; read_not_write == 1; delay < 3;}) begin 
    `uvm_error("body", "randomization failed for req") 
   end 
   finish_item(req); 
     buffer[i] = req.read_data; 
   src_addr = src_addr + 4; // Increment to the next location 
  end 
// Empty the buffer 
  for(int i = 0; i < transfer_size-1; i++) begin 
   start_item(req); 
   if(!req.randomize() with {addr == dst_addr; read_not_write == 0; write_data == buffer[i];delay < 3;}) begin 
    `uvm_error("body", "randomization failed for req") 
   end 
   finish_item(req); 
   dst_addr = dst_addr + 4; // Increment to the next location 
  end 
  dst_addr = dst_start_addr; 
// Check the buffer transfer 
  for(int i = 0; i < transfer_size-1; i++) begin 
   start_item(req); 
   if(!req.randomize() with {addr == dst_addr; read_not_write == 1; write_data == buffer[i];delay < 3;}) begin 
    `uvm_error("body", "randomization failed for req") 
    end 
   finish_item(req); 
   if(buffer[i] != req.read_data) begin 
    `uvm_error("run:", $sformatf("Error in transfer @%0h : Expected %0h, Actual %0h", dst_addr, buffer[i], req.read_data)) 
   end 
   dst_addr = dst_addr + 4; // Increment to the next location 
  end 
  `uvm_info("run:", $sformatf("Finished transfer end addresses SRC: %0h DST:%0h", src_addr, dst_addr), UVM_LOW) 
 endtask: body 
endclass: mem_trans_seq 
// 
// This test shows how to randomize the memory_trans_seq 
// to set it up for a block transfer 
// 
class seq_rand_test extends bus_test_base; 
 `uvm_component_utils(seq_rand_test) 
 function new(string name = "seq_rand_test", uvm_component parent = null); 
  super.new(name); 
 endfunction 
 task run_phase( uvm_phase phase ); phase.raise_objection( this , "start mem_trans_seq" ); 
  mem_trans_seq seq = mem_trans_seq::type_id::create("seq"); 
// Using randomization and constraints to set the initial values 
// 
// This could also be done directly 
// 
  assert(seq.randomize() with {src_addr == 32'h0100_0800; dst_addr inside {[32'h0101_0000:32'h0103_0000]}; transfer_size == 128;}); 
  seq.start(m_agent.m_sequencer); 
  phase.drop_objection( this , "finished mem_trans_seq" ); 
 endtask: run 
endclass: seq_rand_test 

// 
// This class shows how to reuse the values persistent within a sequence 
// It runs the mem_trans_seq once with randomized values and then repeats it 
// several times without further randomization until the memory limit is 
// reached. This shows how the end address values are reused on each repeat. 
// 
class rpt_mem_trans_seq extends bus_seq_base; 
 `uvm_object_utils(rpt_mem_trans_seq) 
 function new(string name = "rpt_mem_trans_seq"); 
  super.new(name); 
 endfunction 
 task body(); 
  mem_trans_seq trans_seq = 
  mem_trans_seq::type_id::create("trans_seq"); 
// First transfer: 
  assert(trans_seq.randomize() with {src_addr inside {[32'h0100_0000:32'h0100_FFFF]}; dst_addr inside {[32'h0103_0000:(32'h0104_0000 - (transfer_size*4))]}; transfer_size < 512; solve transfer_size before dst_addr;}); 
  trans_seq.start(m_sequencer); 
// Continue with next block whilst we can complete within range 
// Each block transfer continues from where the last one left off 
   while ((trans_seq.dst_addr + (trans_seq.transfer_size*4)) < 32'h0104_0000) begin 
   trans_seq.start(m_sequencer); 
  end 
 endtask: body 
endclass: rpt_mem_trans_seq 

// 
// This sequence executes some sub-sequences in a random order 
// 
class rand_order_seq extends bus_seq_base; 
 `uvm_object_utils(rand_order_seq) 
 function new(string name = "rand_order_seq"); 
  super.new(name); 
 endfunction 
// 
// The sub-sequences are created and put into an array of 
// the common base type. 
// 
// Then the array order is shuffled before each sequence is 
// randomized and then executed 
// 
 task body; 
  bus_seq_base seq_array[4]; 
  seq_array[0] = n_m_rw  interleaved_seq::type_id::create("seq_0"); 
  seq_array[1] = rwr_seq::type_id::create("seq_1"); 
  seq_array[2] = n_m_rw_seq::type_id::create("seq_2"); 
  seq_array[3] = fill_memory_seq::type_id::create("seq_3"); 
// Shuffle the array contents into a random order: 
  seq_array.shuffle(); 
// Execute all the array items in turn 
  foreach(seq_array[i]) begin 
   if(!seq_array[i].randomize()) begin 
   `uvm_error("body", "randomization failed for req") 
   end 
   seq_array[i].start(m_sequencer); 
  end 
  endtask: body 
endclass: rand_order_seq