用spinal生成了一个计数器

package mylib

import spinal.core._
import spinal.lib._

import scala.util.Random

// RTL
class MyTopLevel extends Component {
  val io = new Bundle {
    val enable = in  Bool()
    val clear  = in  Bool()
    val cnt    = out UInt(8 bits)
  }

  // seq logic
  val counter = Reg(UInt(8 bits)) init(0)
  when(io.clear) {
    counter := 0
  }.elsewhen(io.enable) {
    counter := counter + 1
  }

  // combinational logic
  io.cnt := counter
}

//Generate Verilog
object MyTopLevelVerilog {
  def main(args: Array[String]) {
    SpinalVerilog(new MyTopLevel)
  }
}

when(condition1){  

}.elsewhen(condition2){

}

cd /etc/yum.repos.d/
curl -L https://www.scala-sbt.org/sbt-rpm.repo > sbt-rpm.repo
yum install sbt

// Generator : SpinalHDL v1.6.4    git head : 598c18959149eb18e5eee5b0aa3eef01ecaa41a1
// Component : MyTopLevel
`timescale 1ns/1ps 
module MyTopLevel (
  input               io_enable,
  input               io_clear,
  output     [7:0]    io_cnt,
  input               clk,
  input               reset
);
  reg        [7:0]    counter;

  assign io_cnt = counter;
  always @(posedge clk or posedge reset) begin
    if(reset) begin
      counter <= 8'h0;
    end else begin
      if(io_clear) begin
        counter <= 8'h0;
      end else begin
        if(io_enable) begin
          counter <= (counter + 8'h01);
        end
      end
    end
  end

endmodule