cordic的FPGA实现（三）、sin、cos函数运算与源码分析

module cordic
(
    input CLOCK,RESET,
   input iCall, 
   output oDone,
   input [31:0]iData,
   output [31:0]cos,
   output [31:0]sin,
   /*
   输出的x为cos值，输出的y为sin值，x=qx，y=qy
   */
   output [31:0]q_deg,q_y,q_x
);
   reg [31:0] atan [15:0];
   //声明atan反正切函数常量表，该常量表从tan（45）度开始每次减小一半儿
   initial begin
       atan[0] = 32'd2949120; atan[1] = 32'd1740992; atan[2] = 32'd919872; atan[3] = 32'd466944;
      atan[4] = 32'd234368; atan[5] = 32'd117312; atan[6] = 32'd58688; atan[7] = 32'd29312; 
      atan[8] = 32'd14656; atan[9] = 32'd7360; atan[10] = 32'd3648; atan[11] = 32'd1856; 
      atan[12] = 32'd896;  atan[13] = 32'd448; atan[14] = 32'd256; atan[15] = 32'd128;
   end
   //带符号位的寄存器声明
   reg signed [31:0]x,y,tx,ty,deg;
   reg [7:0]i;
   reg isDone;
   
   always @ ( posedge CLOCK or negedge RESET )
       if( !RESET )
           begin
            { x,y,tx,ty,deg } <= { 32'd0,32'd0,32'd0,32'd0,32'd0 };
            i <= 8'd0;
            isDone <= 1'b0;
         end
      else if( iCall )
         case( i )
        
             0:
           begin x <= 0.607253 * 65536; y <= 32'd0; deg <= iData << 16; i <= i + 1'b1; end
           
           1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16:
           /*
           在剩余角度大于0时，需要继续逆时针旋转，在单位圆上逆时针旋转的话横坐标会减小，纵坐标会增大
           
           */
           if( deg > 0 )
              begin
                  ty = y >>> i-1;
                  tx = x >>> i-1;
                   x <= x - ty;
                  y <= y + tx;
                  deg <= deg - atan[i-1];
                  i <= i + 1'b1;
              end
           else
           /*
           在剩余角度小于0时候，需要顺时针旋转，顺时针旋转的话纵坐标会减小，横坐标会增大
           */
              begin
                  ty = y >>> i-1;
                  tx = x >>> i-1;
                   x <= x + ty ;
                  y <= y - tx ;
                  deg <= deg + atan[i-1];
                  i <= i + 1'b1;
              end
          
          17:
          begin isDone <= 1'b1; i <= i + 1'b1; end
          
          18:
          begin isDone <= 1'b0; i <= 8'd0; end
             
        endcase
        
    assign oDone = isDone;
    assign cos = x;
    assign sin = y;
    assign { q_deg,q_y,q_x } = { deg,y,x };
    
endmodule

`timescale 1ns/1ns
module cordic_tb;

reg clk;  //系统时钟
reg rst_n;//复位信号
reg iCall;//模块调用信号
reg [31:0]iData; //待求角度
wire oDone;      //迭代完成标志
wire [31:0]cos;  //cos值
wire [31:0]sin;  //sin值
wire [31:0]deg_left; //剩余角度
cordic u0(
.CLOCK(clk),
.RESET(rst_n),
.iCall(iCall), 
.oDone(oDone),
.iData(iData),
.cos(cos),
.sin(sin),
   /*
   输出的x为cos值，输出的y为sin值，x=qx，y=qy
   */
.q_deg(deg_left)
);

initial begin 
clk=0;
forever #5 clk=~clk;
end 

initial begin 
rst_n=0;
#10;
rst_n=1; 
end 

reg [7:0]i;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
 i<=8'd0;
 iCall<=1'b0;
 iData<=32'd0;
end 
else 
case(i) 
0: //z=30
 begin
  if(oDone)
   begin
   iCall<=1'b0;
   i<=i+1'b1;
  end 
   else 
   begin
    iCall<=1'b1;
    iData<=32'd30;
   end 
 end 
1: //z=45
 begin
  if(oDone)
   begin
   iCall<=1'b0;
   i<=i+1'b1;
  end 
   else 
   begin
    iCall<=1'b1;
    iData<=32'd45;
   end  
 end 
2: //z=60
 begin
  if(oDone)
   begin
   iCall<=1'b0;
   i<=i+1'b1;
  end 
   else 
   begin
    iCall<=1'b1;
    iData<=32'd60;
   end  
 end 
3: //z=75
 begin
  if(oDone)
   begin
   iCall<=1'b0;
   i<=i+1'b1;
  end 
   else 
   begin
    iCall<=1'b1;
    iData<=32'd75;
   end  
 end 
4: //z=90
 begin
  if(oDone)
   begin
   iCall<=1'b0;
   i<=i+1'b1;
  end 
   else 
   begin
    iCall<=1'b1;
    iData<=32'd90;
   end 
 end 
 5:
 i<=i;
 endcase  
endmodule