【日更计划085】数字IC基础题【HDL部分】

module half_adder(input_0, input_1, sum, carry);
    input input_0, input_1;
    output sum, carry;
    assign sum = (input_0)^(input_1);
    assign carry = (input_0)&(input_1);
endmodule
 
module full_adder(input_0, input_1, input_2, sum, carry);
    input input_0, input_1, input_2;
    output sum, carry;
    reg sum_intermediate, carry_intermediate_0, carry_intermediate_1;
    half_adder ha1(input0,input1,sum_intermediate,carry_intermediate_0);
    half_adder ha2(sum_intermediate,input2,sum,carry_intermediate_1);
	assign carry = (carry_intermediate_0)|(carry_intermediate_1);
endmodule