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36 篇文章
1
形式验证与formality基本流程
2
安全地启动sequence
3
【UVM COOKBOOK】Testbench Architecture【二】
4
【UVM COOKBOOK】Testbench Architecture【一】
5
svlib文档翻译(第一至四章)
6
svlib文档翻译(第五章)
7
浅谈便携式激励(PSS)和UVM
8
便携式激励vs形式化vsUVM验证方法在IP块的整个生命周期中的比较分析
9
通过字符串访问generate模块内部的变量
10
Verilog:笔试面试常考易错点整理
11
【源码】手把手教你用Python实现Vivado和ModelSim仿真自动化
12
如何快速生成Verilog代码文件列表?(内附开源C代码)
13
IC工程师的通用技能:文本处理
14
NCVerilog+SimVision+Vivado仿真环境搭建
15
串扰
16
论STA | 数字电路中的串扰
17
STA | 串扰,理论分析
18
低功耗 | UPF + CLP
19
combinational clock gating Vs sequential clock gating
20
Clock Domain Crossing, 跨时钟域检查
21
低功耗 | Glitch Power 分析
22
P&R | 如何在实现全流程中考虑IR-Drop
23
点论 | 组合逻辑环 Combinational loop 知多少
24
UVM的一个简单验证demo
25
systemverilog之Automatic
26
【手把手系列】:芯片设计中的Makefile简明教程
27
“ 一网打尽 ” 二进制、格雷码、独热码编码方式
28
分而治之(Hierarchical Sequences),处理复杂事物的绝对准则
29
断言(assertion),把黑盒变成白盒
30
针对assertion based验证的一些“建议”和“不建议”
31
python脚本练习(5):读写文件步骤
32
python脚本练习(4):正则表达式实例
33
python脚本练习(3):正则表达式实例
34
python脚本练习(2):使用正则表达式的三部曲
35
python脚本练习(1):表格打印
36
VCS门级仿真系列文章之sdf文件和$sdf_annotate

P&R | 如何在实现全流程中考虑IR-Drop

随着工艺进步,芯片上的线宽越来越窄,单位电阻也越来越大,而同时设计的复杂度也越来越高,芯片尺寸非但没有减小还长得更大了,以至于绕线越来密集,这对电源完整性提出了新的挑战,维基百科上对电源完整性的定义是:Power integrity: or PI is the analysis to check whether the desired voltage and current are met from source to destination. 对应于数字实现就是IR 跟EM 的分析。对于老工艺,IR 跟EM 在设计末期去修干净即可,但到了新工艺点,如果把IR 跟EM 留到最后再看,是在玩火,因为极可能修不掉需要重头再来。所以亟需在实现早期就去考虑PI, 此处就需要了解一下C 记的IR-Aware 全家桶 —— Innovus + PVS + voltus + Tempus —— 从IR-Aware Placement 到 IR-Aware CCOPT 到reinforce_pg 到Tempus ECO IR drop fixing 到PVS TBF-PG 到Power Grid Optimization.

"Power has to feed every transistor within a chip. That power is distributed around the chip using the metal layers. As fabrication technologies have become smaller, the size of the wires has also been getting smaller, while physical chip dimensions have stayed roughly the same. This means that wires have become thinner but have not gotten shorter. That leads to an increase in resistance per unit length. There is an almost 10X increase in resistance between a 28nm chip and a 7nm chip, and that will follow an exponential increase for smaller geometries. At the same time, the total power consumed by chip has also remained fairly flat.

As current flows through a resistor, the voltage drops – this is what is referred to as IR drop. When the voltage at a transistor drops, it becomes slower and this could impact the circuit timing. When this happens on a critical path through a design, it can also lead to a functional failure and thus needs to be avoided. Another trend in semiconductor design has been a reduction in operating voltage, meaning that small changes in supply voltage may represent an increasing percentage of the digital swing and potentially lead to incorrect logic values being seen.

A second problem is intertwined with IR drop: electromigration. When large currents flow through these thin wires, molecular displacement can happen. This means that molecules of the metal migrate along the wires over time, causing a further shrinking of the wire at certain points and thus an increase in the resistance. So, over time, electromigration can make IR drop worse. It thus becomes necessary to analyze for IR drop over the intended life off the device coupled with electromigration analysis.

IR drop, while causing an increase in delay for a digital transistor, can have an even bigger impact on analog circuitry. Not only can timing change, but it can directly cause functional failures. Given that the current draw of a wire is influenced by activity in other areas of the chip, it is often seen as a source of noise for the analog circuitry and this has to be taken into account when doing circuit analysis."


参考文献:https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000009MqknUAC&pageName=ArticleContent&oMenu=People%20who%20viewed%20this%20also%20viewed

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