核心思想是LFSR
`timescale 1ns / 1ps
//对255取余数
//网上的那个用LUT
//至于说逼近法,我就不考虑了
module div_255(
input dividend,
input clk,
input rst_n,
output [7:0] remainder
);
parameter dividor = 8'hff;
reg [7:0] shifter;
reg [2:0] count;
reg flag;
always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
shifter <= 8'h00;
count <= 3'b000;
flag <= 1'b0;
end
else
begin
if(count==3'b111)
begin
count <= 3'b000;
flag <= 1'b1;
end
else
begin
count <= count + 1'b1;
flag <= 1'b0;
end
shifter[0]<=shifter[7]+dividend;
shifter[1]<=shifter[0]+dividend;
shifter[2]<=shifter[1]+dividend;
shifter[3]<=shifter[2]+dividend;
shifter[4]<=shifter[3]+dividend;
shifter[5]<=shifter[4]+dividend;
shifter[6]<=shifter[5]+dividend;
shifter[7]<=shifter[6]+dividend;
end
end
assign remainder = (flag)?shifter:8'hzz;
endmodule